SH7205 Datasheet, PDF (456/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
• Cycle-stealing transfer mode (transfer through different BIUs)
Bus clock
Single operand transfer
DMAC
Read
Read
Write
Write
CPU
Single operand transfer
Read
Read
Write
Write
[1]
[2] [1]
[2]
• Cycle-stealing transfer mode (transfer through the same BIU)
Bus clock
Single operand transfer
DMAC
Read
Read
Write
Write
CPU
[1]
[2] [1]
[2]
Single operand transfer
Read
Read
Write
Write
[3]
[3]
[3]
• Pipelined transfer mode (transfer through different BIUs)
Bus clock
Single operand transfer
DMAC
Read Read Read Read
Write Write Write Write
CPU
[3]
[3]
[3]
Single operand transfer
Read Read Read Read
Write Write Write Write
[1]
[3]
[2]
[1]
[3]
[2]
This example shows that all DMA transfers ended in one cycle.
Of CPU access cycles, the colored cycles can access any BIUs.
Cycles [1] to [3] indicate the following operating states:
[1]: CPU can access BIUs other than the BIU on the reading side of the DMAC.
[2]: CPU can access BIUs other than the BIU on the writing side of the DMAC.
[3]: CPU can access BIUs other than the BIUs on the reading and writing sides of the DMAC.
Figure 11.3 Example of Bus Mastership Alternation between DMAC and CPU
in Various DMA Transfer Modes
Rev. 1.00 Mar. 25, 2008 Page 424 of 1868
REJ09B0372-0100