SH7205 Datasheet, PDF (647/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4) Timing for Counter Clearing by Compare Match/Input Capture
Figure 12.84 shows the timing when counter clearing on compare match is specified, and figure
12.85 shows the timing when counter clearing on input capture is specified.
Pφ
Compare
match signal
Counter
clear signal
TCNT
N
H'0000
TGR
N
Figure 12.84 Counter Clear Timing (Compare Match)
Pφ
Input capture
signal
Counter clear
signal
TCNT
N
H'0000
TGR
N
Figure 12.85 Counter Clear Timing (Input Capture)
Rev. 1.00 Mar. 25, 2008 Page 615 of 1868
REJ09B0372-0100