SH7205 Datasheet, PDF (12/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

7.3 Register Descriptions......................................................................................................... 161
7.3.1 Interrupt Priority Registers 01, 02, 05 to 21 (C0IPR01, C0IPR02, C0IPR05 to
C0IPR21, C1IPR01, C1IPR02, C1IPR05 to C1IPR21)........................................ 170
7.3.2 Interrupt Control Registers 0 (C0ICR0, C1ICR0) ................................................ 172
7.3.3 Interrupt Control Registers 1 (C0ICR1, C1ICR1) ................................................ 173
7.3.4 Interrupt Control Registers 2 (C0ICR2, C1ICR2) ................................................ 174
7.3.5 IRQ Interrupt Request Registers (C0IRQRR, C1IRQRR).................................... 175
7.3.6 PINT Interrupt Enable Registers (C0PINTER, C1PINTER) ................................ 176
7.3.7 PINT Interrupt Request Registers (C0PIRR, C1PIRR) ........................................ 177
7.3.8 Bank Control Registers (C0IBCR, C1IBCR) ....................................................... 178
7.3.9 Bank Number Registers (C0IBNR, C1IBNR) ...................................................... 179
7.3.10 Inter-Processor Interrupt Control Registers 15 to 08
(C0IPCR15 to C0IPCR08, C1IPCR15 to C1IPCR08).......................................... 180
7.3.11 Inter-processor Interrupt Enable Registers (C0IPER, C1IPER) ........................... 182
7.3.12 Interrupt Enable Control Registers (C0INTER, C1INTER) ................................. 183
7.3.13 IRQ Interrupt Enable Control Registers (C0IRQER, C1IRQER)......................... 184
7.3.14 Interrupt Detect Control Registers (IDCNT6 to IDCNT139) ............................... 185
7.3.15 DMA Transfer Request Enable Registers 0 to 8 (DREQER0 to DREQER8) ...... 190
7.4 Interrupt Sources................................................................................................................ 195
7.4.1 NMI Interrupts ...................................................................................................... 195
7.4.2 User Break Interrupts............................................................................................ 195
7.4.3 H-UDI Interrupts .................................................................................................. 195
7.4.4 IRQ Interrupts....................................................................................................... 196
7.4.5 PINT Interrupts..................................................................................................... 197
7.4.6 On-Chip Peripheral Module Interrupts ................................................................. 198
7.4.7 Inter-Processor Interrupts ..................................................................................... 198
7.5 Interrupt Exception Handling Vector Tables and Priorities............................................... 199
7.6 Operation ........................................................................................................................... 206
7.6.1 Interrupt Operation Sequence ............................................................................... 206
7.6.2 Stack Status after Interrupt Exception Handling................................................... 208
7.7 Interrupt Response Time.................................................................................................... 209
7.8 Register Banks ................................................................................................................... 215
7.9 Register Banks and Bank Control Registers ...................................................................... 216
7.9.1 Bank Save and Restore Operations....................................................................... 216
7.9.2 Save and Restore Operations after Saving to All Banks....................................... 218
7.9.3 Register Bank Exceptions..................................................................................... 219
7.10 Register Bank Error Exception Handling .......................................................................... 219
7.11 Data Transfer with Interrupt Request Signals.................................................................... 220
7.12 Usage Note......................................................................................................................... 220
7.12.1 Timing to Clear an Interrupt Source ..................................................................... 220
Rev. 1.00 Mar. 25, 2008 Page xii of xxxii