SH7205 Datasheet, PDF (1576/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.2.1 Standby Control Register 1 (STBCR1)
STBCR1 is an 8-bit readable/writable register that specifies the states of power-down modes.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
STBY DEEP
SLP
ERE
AXTALE
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R
Initial
Bit Bit Name Value
7
STBY
0
6
DEEP
0
5
SLPERE 0
4
AXTALE 0
3 to 0 
All 0
[Legend]
x: Don't care
R/W
R/W
R/W
R/W
R/W
R
Description
Software Standby, Deep Standby
Specifies transition to software standby mode or deep
standby mode.
0x: Execution of SLEEP instruction by CPU0 puts CPU0
into sleep mode.
10: Execution of SLEEP instruction by CPU0 puts the chip
in software standby mode.
11: Execution of SLEEP instruction by CPU0 puts the chip
in deep standby mode.
Sleep Error Enable
Enables or disables to generate a sleep error exception.
After a sleep error exception is generated with this bit set to
1, be sure to clear this bit to 0 in the interrupt exception
handling routine.
0: Sleep error exception is disabled.
1: Sleep error exception is enabled.
Audio Crystal Resonator Enable
Enables or disables the functions of the crystal resonator for
audio.
0: Crystal resonator functions are enabled.
1: Crystal resonator functions are disabled.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1544 of 1868
REJ09B0372-0100