SH7205 Datasheet, PDF (654/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is
activated, the flag is cleared automatically. Figure 12.96 shows the timing for status flag clearing
by the CPU, and figure 12.97 shows the timing for status flag clearing by the DMAC.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 12.96 Timing for Status Flag Clearing by CPU
Pφ, Bφ
DMAC read cycle
DMAC write cycle
Address
Source address
Destination
address
Status flag
Interrupt
request signal
Flag clear
signal
Figure 12.97 Timing for Status Flag Clearing by DMAC Activation
Rev. 1.00 Mar. 25, 2008 Page 622 of 1868
REJ09B0372-0100