SH7205 Datasheet, PDF (1591/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.2.16 System Control Register 9 (SYSCR9)
SYSCR9 is an 8-bit readable/writable register that enables or disables access (read/write) from
CPU1 to each page of the high-speed on-chip RAM1. Other descriptions on this register are the
same as SYSCR1.
Note: When writing to this register, see section 30.4, Usage Notes.
30.2.17 System Control Register 10 (SYSCR10)
SYSCR10 is an 8-bit readable/writable register that enables or disables writing from CPU1 to each
page of the high-speed on-chip RAM1. Other descriptions on this register are the same as
SYSCR2.
Note: When writing to this register, see section 30.4, Usage Notes.
30.2.18 System Control Register 11 (SYSCR11)
SYSCR11 is an 8-bit readable/writable register that enables or disables access (read/write) from
the DMAC to each page of the high-speed on-chip RAM1. Other descriptions on this register are
the same as SYSCR1.
Note: When writing to this register, see section 30.4, Usage Notes.
30.2.19 System Control Register 12 (SYSCR12)
SYSCR12 is an 8-bit readable/writable register that enables or disables writing from the DMAC to
each page of the high-speed on-chip RAM1. Other descriptions on this register are the same as
SYSCR2.
Note: When writing to this register, see section 30.4, Usage Notes.
Rev. 1.00 Mar. 25, 2008 Page 1559 of 1868
REJ09B0372-0100