SH7205 Datasheet, PDF (251/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.9.3 Register Bank Exceptions
There are two types of register bank exceptions (register bank errors): register bank overflow and
register bank underflow.
(1) Register Bank Overflow
This exception occurs if, after data has been saved to all of the register banks, the CPU accepts an
interrupt and the use of the register banks is enabled for that interrupt, and the BOVE bits in the
bank number registers (C0IBNR and C1IBNR) are set to 1. In this case, the bank number bits
(BN) in the bank number registers (C0IBNR and C1IBNR) remain set to the bank count of 15 and
saving to the register bank is not performed.
(2) Register Bank Underflow
This exception occurs if the RESBANK (restore from register bank) instruction is executed when
no data has been saved to the register banks. In this case, the values of R0 to R14, GBR, MACH,
MACL, and PR do not change. In addition, the bank number bits (BN) in the bank number
registers (C0IBNR and C1IBNR) remain set to 0.
7.10 Register Bank Error Exception Handling
When a register bank error occurs, register bank error exception handling starts. When this
happens, the CPU operates as follows:
1. The exception service routine start address is fetched from the exception handling vector table
corresponding to the register bank error that has occurred.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. For a register bank overflow, the saved PC
value is the start address of the instruction to be executed after the last executed instruction.
For a register bank underflow, the saved PC value is the start address of the executed
RESBANK instruction. To prevent multiple interrupts from occurring at a register bank
overflow, the priority level of the interrupt that caused the register bank overflow is written to
the interrupt mask level bits (I3 to I0) of the status register (SR).
4. Program execution starts from the exception service routine start address.
Rev. 1.00 Mar. 25, 2008 Page 219 of 1868
REJ09B0372-0100