SH7205 Datasheet, PDF (311/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Bit
18, 17
Bit Name

16
WRMOD
15 to 0 
Initial
Value R/W Description
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W Write Access Mode Select
This bit selects operating mode for write access. Clearing
WRMOD to 0 selects byte-write strobe mode. In this
mode, data writes are controlled by multiple write signals
(WE3 to WE0) that correspond to the individual byte
positions. Setting WRMOD to 1 selects one-write strobe
mode. In this mode, data writes are controlled by multiple
byte control signals (BC3 to BC0) that correspond to the
individual byte positions and a single write signal (WE).
0: Byte-write strobe mode
1: One-write strobe mode
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Writing to the CSn mode register (CSMODn) must be done while the CSC for the corresponding
channel is disabled (EXENB = 0). Only channel 0 (CS0) is allowed for writing to the register
without disabling the CSC (EXENB = 1). To write to CSMOD0 with CSC enabled, satisfy all of
the following conditions:
1. Stop the DMAC.
2. Keep the CPU other than the one that is going to rewrite the register from accessing CS0
(including access for instruction fetch). For example, if CPU0 is going to rewrite the register,
make CPU1 stay looping by a program copied to on-chip memory, or put CPU1 in a sleep
state.
3. Do not perform data write access to CS0 after a reset is released but before the register is
updated.
Rev. 1.00 Mar. 25, 2008 Page 279 of 1868
REJ09B0372-0100