SH7205 Datasheet, PDF (1782/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 32 List of Registers
Module Register
Power-On Manual Deep
Software Module
Name Abbreviation Reset
Reset
Standby Standby Standby Sleep
Power-
Down
Modes
STBCR7
CSTBCR1
SYSCR1
Initialized Retained Initialized Retained 
Initialized Retained Initialized Retained 
Initialized Retained Initialized Retained 
Retained
Retained
Retained
SYSCR2
Initialized Retained Initialized Retained 
Retained
SYSCR3
Initialized Retained Initialized Retained 
Retained
SYSCR4
Initialized Retained Initialized Retained 
Retained
SYSCR5
Initialized Retained Initialized Retained 
Retained
SYSCR6
Initialized Retained Initialized Retained 
Retained
SYSCR7
Initialized Retained Initialized Retained 
Retained
SYSCR8
Initialized Retained Initialized Retained 
Retained
SYSCR9
Initialized Retained Initialized Retained 
Retained
SYSCR10 Initialized Retained Initialized Retained 
Retained
SYSCR11 Initialized Retained Initialized Retained 
Retained
SYSCR12 Initialized Retained Initialized Retained 
Retained
SWRSTCR Initialized Retained Initialized Retained 
Retained
HIZCR
Initialized Retained Initialized Retained 
Retained
C0MSR
Initialized Initialized Initialized Initialized 
Initialized
C1MSR
Initialized Initialized Initialized Initialized 
Initialized
RRAMKP
Initialized Retained Initialized Retained 
Retained
DSCTR
Initialized Retained Retained Retained 
Retained
DSSSR
Initialized Retained Initialized Retained 
Retained
DSFR
H-UDI*⁷ SDIR
Initialized Retained Retained Retained 
Retained
Retained Retained Initialized Retained Retained Retained
Notes: 1. Retains the previous value after an internal power-on reset by means of the WDT.
2. The BN3 to BN0 bits are initialized.
3. Counting up continues.
4. Bits RTCEN and START are retained.
5. Bits BC3 to BC0 are initialized.
6. Since pin states are read out on the port G data register (PGDRL) and the port
registers, values in these registers are neither retained nor initialized.
7. Initialized by TRST assertion or in the Test-Logic-Reset state of the TAP controller.
Rev. 1.00 Mar. 25, 2008 Page 1750 of 1868
REJ09B0372-0100