SH7205 Datasheet, PDF (451/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.24 DMA Reload Two-Dimensional Addressing Block Setting Register
(DMR2DBLKm)
DMR2DBLKm is a register used to set the number of blocks to be reloaded to the DMA two-
dimensional addressing block setting register (DM2DBLKm). To enable the reload function, set
the two-dimensional reload function enable bit (2DRLOD) of DMA control register A
(DMCNTAm) to 1. When enabled, it is necessary to set both the DMA two-dimensional
addressing block setting register (DM2DBLKn) and DMA reload two-dimensional addressing
block setting register (DMR2DBLKm).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
DRBN[23:16]
Initial value: 0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DRBN[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 24 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
23 to 0 DRBN
[23:0]
Undefined R/W DMA Block Count for Reloading
These bits are used to set the number of blocks in one line
to be reloaded to the DMA two-dimensional addressing
block setting register.
00000000_00000000_00000000: 1 block
:
11111111_11111111_11111111: 16777216 blocks
Rev. 1.00 Mar. 25, 2008 Page 419 of 1868
REJ09B0372-0100