SH7205 Datasheet, PDF (1596/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.2.23 Data Retention On-Chip RAM Area Specification Register (RRAMKP)
RRAMKP is an 8-bit readable/writable register specifies whether to retain the contents of the
corresponding area of the on-chip RAM (for data retention) in deep standby mode.
When the RRAMKP bit is set to 1, the contents of the corresponding area of the on-chip RAM are
retained in deep standby mode. When the bit is cleared to 0, the contents of the corresponding area
of the on-chip RAM are not retained in deep standby mode.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
RRAM RRAM RRAM RRAM
KP3 KP2 KP1 KP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W
Bit
7 to 4
3
2
1
Initial
Bit Name Value

All 0
RRAMKP3 0
RRAMKP2 0
RRAMKP1 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RRAM Storage Area 3 (page 3* of on-chip RAM for data
retention)
0: The contents of the corresponding on-chip RAM area are
not retained in deep standby mode.
1: The contents of the corresponding on-chip RAM area are
retained in deep standby mode.
R/W RRAM Storage Area 2 (page 2* of on-chip RAM for data
retention)
0: The contents of the corresponding on-chip RAM area are
not retained in deep standby mode.
1: The contents of the corresponding on-chip RAM area are
retained in deep standby mode.
R/W RRAM Storage Area 1 (page 1* of on-chip RAM for data
retention)
0: The contents of the corresponding on-chip RAM area are
not retained in deep standby mode.
1: The contents of the corresponding on-chip RAM area are
retained in deep standby mode.
Rev. 1.00 Mar. 25, 2008 Page 1564 of 1868
REJ09B0372-0100