SH7205 Datasheet, PDF (217/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.14 Interrupt Detect Control Registers (IDCNT6 to IDCNT139)
IDCNT6 to IDCNT139 (except IDCNT65 and 127 to 129) are 16-bit registers that control whether
to enable interrupt requests from on-chip peripheral modules and also control which CPU should
accept the requests.
Table 7.7 shows the correspondence between the sources of on-chip peripheral module interrupt
requests and the IDCNT registers.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
- CPUN INTEN -
-
- MON -
-
-
-
Initial value: 0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
15

0
14

1
13 to 10 
All 0
9
CPUN
0
8
INTEN 1
R/W Description
R
Reserved
This bit is always read as 0. The write value should always
be 0.
R
Reserved
This bit is always read as 1. The write value should always
be 1.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W CPU Accepting Interrupt Request
This bit specifies which CPU should accept interrupt
requests from on-chip peripheral modules.
0: CPU0 accepts interrupt request from on-chip peripheral
module.
1: CPU1 accepts interrupt request from on-chip peripheral
module.
R/W Interrupt Request Input Enable
This bit enables or disables acceptance of interrupt
requests from on-chip peripheral modules.
0: Interrupt request input from on-chip peripheral module is
disabled.
1: Interrupt request input from on-chip peripheral module is
enabled.
Rev. 1.00 Mar. 25, 2008 Page 185 of 1868
REJ09B0372-0100