SH7205 Datasheet, PDF (718/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
14.3 Register Descriptions
The WDT has the following registers.
Table 14.2 Register Configuration
Register Name
Abbreviation R/W
Initial
Value
Address
Watchdog timer counter 0
WTCNT0
R/W H'00
H'FFFE0002
Watchdog timer control/status
register 0
WTCSR0
R/W H'18
H'FFFE0000
Watchdog reset control/status
register 0
WRCSR0
R/W H'1F
H'FFFE0004
Watchdog timer counter 1
WTCNT1
R/W H'00
H'FFFE000A
Watchdog timer control/status
register 1
WTCSR1
R/W H'18
H'FFFE0008
Watchdog reset control/status
register 1
WRCSR1
R/W H'3F
H'FFFE000C
Note: * For the access size, see section 14.3.4, Notes on Register Access.
Access
Size
16*
16*
16*
16*
16*
16*
14.3.1 Watchdog Timer Counter (WTCNT0, WTCNT1)
WTCNT is an 8-bit readable/writable register that is incremented by cycles of the selected clock
signal. When an overflow occurs, it generates a watchdog timer overflow signal (WDTOVF) in
watchdog timer mode and an interrupt in interval timer mode.
Use word access to write to WTCNT with H'5A set in the upper byte. Use byte access to read
from WTCNT.
Note: The method for writing to WTCNT differs from that for other registers to prevent
erroneous writes. See section 14.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Mar. 25, 2008 Page 686 of 1868
REJ09B0372-0100