SH7205 Datasheet, PDF (11/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling ...........................................................................135
6.1 Overview............................................................................................................................ 135
6.1.1 Types of Exception Handling and Priority............................................................ 135
6.1.2 Exception Handling Operations ............................................................................ 137
6.1.3 Exception Handling Vector Table......................................................................... 139
6.2 Resets ................................................................................................................................. 141
6.2.1 Input/Output Pins.................................................................................................. 141
6.2.2 Types of Reset ...................................................................................................... 141
6.2.3 Power-On Reset .................................................................................................... 142
6.2.4 Manual Reset ........................................................................................................ 144
6.3 Address Errors ................................................................................................................... 145
6.3.1 Address Error Sources .......................................................................................... 145
6.3.2 Address Error Exception Handling ....................................................................... 146
6.4 Register Bank Errors.......................................................................................................... 147
6.4.1 Register Bank Error Sources................................................................................. 147
6.4.2 Register Bank Error Exception Handling ............................................................. 147
6.5 Sleep Errors........................................................................................................................ 148
6.5.1 Sleep Error Source ................................................................................................ 148
6.5.2 Sleep Error Exception Handling ........................................................................... 148
6.6 Interrupts............................................................................................................................ 149
6.6.1 Interrupt Sources................................................................................................... 149
6.6.2 Interrupt Priority Level ......................................................................................... 149
6.6.3 Interrupt Exception Handling ............................................................................... 150
6.7 Exceptions Triggered by Instructions ................................................................................ 151
6.7.1 Types of Exceptions Triggered by Instructions .................................................... 151
6.7.2 Trap Instruction..................................................................................................... 152
6.7.3 Slot Illegal Instructions ......................................................................................... 152
6.7.4 General Illegal Instructions................................................................................... 152
6.7.5 Integer Division Exceptions.................................................................................. 153
6.7.6 FPU Exceptions .................................................................................................... 153
6.8 When Exception Sources Are Not Accepted ..................................................................... 155
6.9 Stack Status after Exception Handling Ends...................................................................... 156
6.10 Usage Notes ....................................................................................................................... 158
6.10.1 Value of Stack Pointer (SP) .................................................................................. 158
6.10.2 Value of Vector Base Register (VBR) .................................................................. 158
6.10.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 158
Section 7 Interrupt Controller (INTC) ...............................................................159
7.1 Features.............................................................................................................................. 159
7.2 Input/Output Pins ............................................................................................................... 161
Rev. 1.00 Mar. 25, 2008 Page xi of xxxii