SH7205 Datasheet, PDF (1234/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W Description
15
OVRN
0
R/W* Overrun/Underrun Detection Status
This bit is set when an overrun or underrun has been
detected in the pipe during isochronous transfer.
On detection of an overrun or underrun, an NRDY
interrupt request is generated.
For details, see section 24.3.23, NRDY Interrupt
Status Register (NRDYSTS).
[When the host controller function is selected]
This module sets this bit to 1 on any of the following
conditions.
• For the isochronous transfer pipe in the
transmitting direction, the time to issue an OUT
token comes before all the transmit data has
been written to the FIFO buffer.
• For the isochronous transfer pipe in the receiving
direction, the time to issue an IN token comes
when no FIFO buffer planes are empty.
[When the function controller function is selected]
This module sets this bit to 1 on any of the following
conditions.
• For the isochronous transfer pipe in the
transmitting direction, the IN token is received
before all the transmit data has been written to
the FIFO buffer.
• For the isochronous transfer pipe in the receiving
direction, the OUT token is received when no
FIFO buffer planes are empty.
0: No error
1: An error occurred
Note: This bit is for debugging. The system should
be designed such that overruns or underruns
do not occur.
Rev. 1.00 Mar. 25, 2008 Page 1202 of 1868
REJ09B0372-0100