SH7205 Datasheet, PDF (155/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
5.4 Register Descriptions
The clock pulse generator has the following registers.
Table 5.4 Register Configuration
Register Name Abbreviation R/W
Frequency
FRQCR0
R/W
control register _FRQCR1
R/W
Initial Value
Clock Modes 0, 1, 2 Clock Mode 3
H'0124
H'0215
H'0020
H'0010
Address
Access
Size
H'FFFE0010 16
H'FFFE0012 16
5.4.1 Frequency Control Registers 0 and 1 (FRQCR0 and FRQCR1)
(1) FRQCR0
FRQCR0 is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin during normal operation mode, changes in the multiplication rate of the PLL circuit,
software standby mode, and standby mode cancellation. The register also specifies the frequency
multiplication rate of the PLL circuit and the frequency division ratio for the CPU0 internal clock
(I₀φ) and peripheral clock (Pφ). The FRQCR0 register should be changed only from CPU0.
Bit: 15 14 13 12 11
-
CKO
EN2
CKOEN[1:0]
-
Initial value: 0
0
0
0
0
R/W: R R/W R/W R/W R
10 9
8
7
-
STC[1:0]
-
0 0/1* 0/1* 0
R R/W R/W R
6
5
4
3
2
1
0
-
IFC[1:0]
-
PFC[2:0]
0 0/1* 0/1* 0
1
0 0/1*
R R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
Rev. 1.00 Mar. 25, 2008 Page 123 of 1868
REJ09B0372-0100