SH7205 Datasheet, PDF (1432/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(8) RGB Conversion of External Input Moving Picture
The timing relations between the output data and clock signal from the external video decoder, i.e.
the VICLK, VICLKENB, and VIDATA[7:0] are shown in figure 26.15.
Since the data is in YCbCr422 pixel format and the output data is to be composed with graphics
(RGB) data, conversion is initially from YCbCr422 to YCbCr444, and then from YCbCr to RGB.
VICLK (27MHz)
VICLKENB
VIDATA[7:0] ^{Invalid Invalid Cb0}
Y0
Cr0
Y1
Cb1
Y2
Cr1
Y3
Cb2
Y4
DVAL_PR (Internal)
YDATA[7:0] (Internal) ^{Invalid Y0}
Y1
Y2
Y3
CbDATA[7:0] (Internal) ^{Invalid Cb0}
Cb0
Cb1
Cb1
CrDATA[7:0] (Internal) ^{Invalid Cr0}
Cr0
Cr1
Cr1
ENA_DAT (Internal)
Cb0 and Cr0 can be repalaced with each other by setting 1
in the CBCR bit of the MGR_MIXMODE register (Cb0 → Cr0/Cr0 → Cb0).
Figure 26.15 Timing of Conversion from YCbCr422 to YCbCr444
The formulae for converting from YCbCr to RGB are given below.
R = 1.164(Y-16) + 1.596 (Cr – 128)
G = 1.164 (Y-16) – 0.391 (Cb – 128) – 0.813 (Cr – 128)
B = 1.164 (Y-16) + 2.018 (Cb-128)
Rev. 1.00 Mar. 25, 2008 Page 1400 of 1868
REJ09B0372-0100