SH7205 Datasheet, PDF (1007/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
In Event Triggered Mode RCAN-TL1 will clear a transmit pending flag after successful
transmission of its corresponding message or when a transmission abort is requested successfully
from the TXCR. In Time Trigger Mode, TXPR for the Mailboxes from 30 to 24 is NOT cleared
after a successful transmission, in order to keep transmitting at each programmed basic cycle. The
TXPR flag is not cleared if the message is not transmitted due to the CAN node losing the
arbitration process or due to errors on the CAN bus, and RCAN-TL1 automatically tries to
transmit it again unless its DART bit (Disable Automatic Re-Transmission) is set in the Message-
Control of the corresponding Mailbox. In such case (DART set), the transmission is cleared and
notified through Mailbox Empty Interrupt Flag (IRR8) and the correspondent bit within the Abort
Acknowledgement Register (ABACK).
If the status of the TXPR changes, the RCAN-TL1 shall ensure that in the identifier priority
scheme (MCR2 = 0), the highest priority message is always presented for transmission in an
intelligent way even under circumstances such as bus arbitration losses or errors on the CAN bus.
Please refer to the Application Note for details.
When the RCAN-TL1 changes the state of any TXPR bit position to a '0', an empty slot interrupt
(IRR8) may be generated. This indicates that either a successful or an aborted mailbox
transmission has just been made. If a message transmission is successful it is signalled in the
TXACK register, and if a message transmission abortion is successful it is signalled in the
ABACK register. By checking these registers, the contents of the Message of the corresponding
Mailbox may be modified to prepare for the next transmission.
• TXPR1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TXPR1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * It is possible only to write a ‘1’ for a Mailbox configured as transmitter.
Bit 15 to 0 — Requests the corresponding Mailbox to transmit a CAN Frame. The bit 15 to 0
corresponds to Mailbox-31 to 16 respectively. When multiple bits are set, the order of the
transmissions is governed by the MCR2 – CAN-ID or Mailbox number.
Rev. 1.00 Mar. 25, 2008 Page 975 of 1868
REJ09B0372-0100