SH7205 Datasheet, PDF (1606/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
(2) Canceling Software Standby Mode
Software standby mode is canceled by an interrupt (NMI and IRQ) or a reset (power-on reset or
manual reset).
(a) Canceling by an interrupt
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE)
in interrupt control register 0 (C0ICR0, C1ICR0) of the interrupt controller (INTC)) or the falling
edge or rising edge of an IRQ pin (IRQ7 to IRQ0) (selected by the IRQn sense select bits (IRQn1S
and IRQn0S) in interrupt control register 1 (C0ICR1, C1ICR1) of INTC) is detected, clock
oscillation is started. This clock pulse is supplied only to the oscillation settling counter (WDT)
used to count the oscillation settling time.
After the elapse of the time set in the clock select bits (CKS[2:0]) in the watchdog timer
control/status register (WTCSR0) of WDT0 before the transition to software standby mode, the
WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, the clock
pulse will be supplied to the entire chip after this overflow. After software standby mode is thus
canceled and NMI interrupt exception handling (IRQ interrupt exception handling in case of IRQ)
is executed, the LSI enters dual-processor mode.
When canceling software standby mode by the NMI interrupt or IRQ interrupt, set the CKS[2:0]
bits so that the WDT overflow period will be equal to or longer than the oscillation settling time.
The clock output phase of the CKIO pin may be unstable or fixed to low level immediately after
an interrupt is detected and until software standby mode in canceled. When software standby
mode is canceled by the falling edge of the NMI pin, the NMI pin should be high when the CPU
enters software standby mode (when the clock pulse stops) and should be low when the CPU
returns from software standby mode (when the clock is initiated after the oscillation settling).
When software standby mode is canceled by the rising edge of the NMI pin, the NMI pin should
be low when the CPU enters software standby mode (when the clock pulse stops) and should be
high when the CPU returns from software standby mode (when the clock is initiated after the
oscillation settling). (This is the same with the IRQ pin.)
(b) Canceling by a reset
When the RES pin or MRES pin is driven low, the LSI enters the power-on reset or manual reset
state and software standby mode is canceled. After that, the reset exception handling is executed
and then the LSI enters dual-processor mode.
Keep the RES pin or MRES pin low until the clock oscillation settles.
Rev. 1.00 Mar. 25, 2008 Page 1574 of 1868
REJ09B0372-0100