SH7205 Datasheet, PDF (1820/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 33 Electrical Characteristics
33.4.8 SCIF Timing
Table 33.13 SCIF Timing
Conditions:VCC = PLLVCC = 1.1 to 1.3 V, USBDVCC = 1.1 to 1.3 V, USBAVCC = 1.1 to 1.3 V,
PVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAPVCC = 3.0 to 3.6 V,
2DGAPVCC0 = 3.0 to 3.6 V, 2DGAPVCC1 = 3.0 to 3.6 V,
VSS = PLLVSS = USBAVSS = AVSS = USBAPVSS = 2DGAPVSS0 = 2DGAPVSS1 = 0 V,
Ta = −20 to 85 °C
Item
Symbol Min.
Max.
Input clock cycle (clocked synchronous) t
12
Scyc

(asynchronous)
4

Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(clocked synchronous)
t
SCKr
t_SCKf
t_SCKW
t_TXD


0.4

1.5
1.5
0.6
3 t_pcyc + 15
Receive data setup time
(clocked synchronous)
t
RXS
4
t
pcyc
+
15

Receive data hold time
(clocked synchronous)
t
RXH
1
t
pcyc
+
15

Note: t_pcyc indicates the peripheral clock (Pφ) cycle.
Unit
t
pcyc
t_pcyc
t
pcyc
t_pcyc
t_Scyc
ns
ns
ns
Figure
Figure 33.29
Figure 33.29
Figure 33.29
Figure 33.29
Figure 33.29
Figure 33.30
Figure 33.30
Figure 33.30
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 33.29 SCK Input Clock Timing
Rev. 1.00 Mar. 25, 2008 Page 1788 of 1868
REJ09B0372-0100