SH7205 Datasheet, PDF (1254/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.36 Pipe Configuration Register (PIPECFG)
PIPECFG is a register that specifies the transfer type, buffer memory access direction, and
endpoint numbers for PIPE1 to PIPE9. It also selects continuous or non-continuous transfer mode,
single or double buffer mode, and whether to continue or disable pipe operation at the end of
transfer.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
TYPE[1:0]
—
—
—
BFRE
DBLB CNTMD
SHT
NAK
—
Initial value: 0
0
-
-
-
0
0
0
0
-
R/W: R/W R/W R
R
R R/W R/W R/W R/W R
5
4
3
2
1
0
— DIR
EPNUM[3:0]
-
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Bit Name
15, 14 TYPE[1:0]
Initial
Value R/W
00
R/W
Description
Transfer Type*
Selects the transfer type for the pipe selected by the
PIPESEL bits (selected pipe)
• PIPE1 and PIPE2
00: Pipe disabled
01: Bulk transfer
10: Setting prohibited
11: Isochronous transfer
• PIPE3 to PIPE5
00: Pipe disabled
01: Bulk transfer
10: Setting prohibited
11: Setting prohibited
• PIPE6 to PIPE9
00: Pipe disabled
01: Setting prohibited
10: Interrupt transfer
11: Setting prohibited
Note: Before setting PID to BUF, be sure to set these
bits to the value other than 00.
Rev. 1.00 Mar. 25, 2008 Page 1222 of 1868
REJ09B0372-0100