SH7205 Datasheet, PDF (1235/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name Value
R/W
14
CRCE
0
R/W*
13 to 11 
Undefined R
10 to 0 FRNM[10:0] H'000
R
Note: * Only 0 can be written to.
Description
Receive Data Error
This bit is set when a CRC error or bit stuffing error
has been detected in the pipe during isochronous
transfer. At the same time, an NRDY interrupt
request is generated. For details, see section
24.3.23, NRDY Interrupt Status Register
(NRDYSTS).
0: No error
1: An error occurred
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Frame Number
The latest frame number can be confirmed. The
frame number is updated every time an SOF packet
is issued or received (every 1 ms).
Note: When reading these bits, read twice and make
sure that the same value is read.
Rev. 1.00 Mar. 25, 2008 Page 1203 of 1868
REJ09B0372-0100