SH7205 Datasheet, PDF (1371/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
• Each SBHF_STAT bit changes from 0 to 1 when the corresponding buffer SB1 or SB2 is full
or when the amount of pixel data in the SB buffer coincides with the specified number of
pixels.
Furthermore, the SBHF_STAT bit changes from 1 to 0 on completion of reading the data in
the corresponding half of SB buffer (or the data remaining herein).
• Each SAHF_STAT bit changes from 0 to 1 when the corresponding buffer SA1 or SA2 is full
or when the amount of pixel data in the SA buffer coincides with the specified number of
pixels.
Furthermore, the SAHF_STAT bit changes from 1 to 0 on completion of reading the data in
the corresponding half of SA buffer (or the data remaining herein).
• "Coincide" in the above list means that the width setting in register GR_SABSET,
GR_DCSET, or MGR_SESET matches the number of data transferred to or from the relevant
buffer or that the corresponding half of the double-buffer is full.
• If an abnormal state arises, such as stopping of graphics operations before they are completed,
use this register identify the cause of the problem.
 If the SB_REND or SA_REND bit is being held at 1, check the settings of registers related
to buffer DC (for example, the value of GR_DCSET).
 If the SB_REND or SA_REND bit is being held at 0, and one buffer of the SB and SA
double-buffers remains full, check the settings of registers related to buffers SB and SA
(for example, the value of GR_SABSET).
 If the blitter is reactivated, write 1 to bits SB_STEN and SA_STEN in register
GR_BLTPLY.
 If buffer SE is empty, write 0 to bits OUTEN and EXTEN in register GR_MIXPLY.
Output can then be restarted.
Rev. 1.00 Mar. 25, 2008 Page 1339 of 1868
REJ09B0372-0100