SH7205 Datasheet, PDF (1492/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(3) Summary of Output Block Operations
As a summary of output block operations, the text below provides an example where data equal to
the specified number of pixels is transferred from output plane PX, which is written in an arbitrary
memory space on the SDRAM, to the SE buffer using the DMAC, and the data is blended with
moving pictures before being output.
The area for memory plane PX is set as follows: the number of lines in the SEHIGH bits of the
MGR_SESET register, and the number of pixels in the SEWIDH bits of the GR_SESET register.
Starting address
of the PX area
(word address)
PX write area SEWIDH
(number of pixels)
PX write area
SEHIGH
(number of lines)
Target PX area
A
B
DMA transfer
for n times
Line pitch (64-byte boundary)
SE
buffer
Output block
Valid number of pixels
of moving picture
(720 pixels)
Valid number of lines
of moving picture
(one frame = 525 lines)
Moving-picture input
Blending
in the output
block in units of
data written to the
input buffer
RGB
output
Horizontal
resizing
SEWIDH (Number of pixels)
Synthesized image
A
B
SEHIGH
(Number of lines)
Figure 26.54 Summary of Output Block Operations
The SE buffer has a 960-byte double-buffer structure (SE1, SE2). For example, if the following
values are assigned: SEWIDH bits = 480 (pixels) in the MGR_SESET register and SEHIGH bits =
240 (lines) in the MGR_SESET register, and if the OUTEN bit = 1 in the GR_MIXPLY register to
enable graphics display, output block operations work as follows:
1. Transfers the first 480 pixels to SE1 (SEHF_STAT (0) = 1), followed by VIVSYNC input,
constant-rate output processing, and output to the panel unit.
2. Transfers the next 480 pixels to SE2 (SEHF_STAT (1) = 1), followed by VIVSYNC input,
constant-rate output processing, and output to the panel unit.
Rev. 1.00 Mar. 25, 2008 Page 1460 of 1868
REJ09B0372-0100