SH7205 Datasheet, PDF (1328/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
In response to tokens that are shaded in the figure, responses occur based on the buffer memory
status.
1. IN direction:
 If the buffer is in the transmission enabled state, the data is transferred as a normal
response.
 If the buffer is in the transmission disabled state, a zero-length packet is sent and an
underrun error occurs.
2. OUT direction:
 If the buffer is in the reception enabled state, the data is received as a normal response.
 If the buffer is in the reception disabled state, the data is discarded and an overrun error
occurs.
SOF
Normal transfer
Token corrupted
Packet inserted
Frame misaligned
Frame misaligned
Token delayed
Token
Token
Token
Token
Token
Token
Token
Token
Token
1
Token
1 Token
Token
1 Token
Token
Token
Token
Token
1 Token
1 Token
Token
Token
Token
1
1
Token
Figure 24.16 Example of an Interval Error Being Generated when IITV = 1
Rev. 1.00 Mar. 25, 2008 Page 1296 of 1868
REJ09B0372-0100