SH7205 Datasheet, PDF (177/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.3 Address Errors
6.3.1 Address Error Sources
Address errors occur when instructions are fetched or data read or written, as shown in table 6.7.
Table 6.7 Bus Cycles and Address Errors
Bus Cycle
Type
Bus
Master Bus Cycle Description
Address Errors
Instruction
fetch
CPU
An instruction is fetched from an even address.
An instruction is fetched from an odd address.
None (normal)
Address error
An instruction is fetched from other than H'F0000000 None (normal)
to H'F5FFFFFF in cache address array space*.
An instruction is fetched from H'F0000000 to
H'F5FFFFFF in cache address array space*.
Address error
Data
read/write
CPU
Word data is accessed from an even address.
Word data is accessed from an odd address.
None (normal)
Address error
Longword data is accessed from a longword
boundary.
None (normal)
Longword data is accessed from other than a long- Address error
word boundary.
Byte or word data is accessed in on-chip peripheral None (normal)
module space*.
Longword data is accessed in 16-bit on-chip
peripheral module space*.
None (normal)
Longword data is accessed in 8-bit on-chip
peripheral module space*.
None (normal)
Note: * See section 9, Cache, for details of the address array space of cache.
Rev. 1.00 Mar. 25, 2008 Page 145 of 1868
REJ09B0372-0100