SH7205 Datasheet, PDF (1667/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 32 List of Registers
Module
Name Register Name
Abbreviation
Number
of Bits Address
RCAN- Tx-Trigger Time Selection
TL1
Register_0
TTTSEL_0
16
H'FFFE50A4
Mailbox n Control 0_H_0
(n = 0 to 31)
MBn_CONTROL0_H_0 16
(n = 0 to 31)
H'FFFE5100
+ n × 32
Mailbox n Control 0_L_0
(n = 0 to 31)
MBn_CONTROL0_L_0 16
(n = 0 to 31)
H'FFFE5102
+ n × 32
Mailbox n Local Acceptance Filter MBn_LAFM0_0
Mask 0_0 (n = 0 to 31)
(n = 0 to 31)
16
H'FFFE5104
+ n × 32
Mailbox n Local Acceptance Filter MBn_LAFM1_0
Mask 1_0 (n = 0 to 31)
(n = 0 to 31)
16
H'FFFE5106
+ n × 32
Mailbox n Data 01_0 (n = 0 to 31) MBn_DATA_01_0
16
(n = 0 to 31)
H'FFFE5108
+ n × 32
Mailbox n Data 23_0 (n = 0 to 31) MBn_DATA_23_0
16
(n = 0 to 31)
H'FFFE510A
+ n × 32
Mailbox n Data 45_0 (n = 0 to 31) MBn_DATA_45_0
16
(n = 0 to 31)
H'FFFE510C
+ n × 32
Mailbox n Data 67_0 (n = 0 to 31) MBn_DATA_67_0
16
(n = 0 to 31)
H'FFFE510E
+ n × 32
Mailbox n Control 1_0 (n = 0 to 31) MBn_CONTROL1_0 16
(n = 0 to 31)
H'FFFE5110
+ n × 32
Mailbox n Time Stamp_0
(n = 0 to 15, 30, 31)
MBn_TIMESTAMP_0 16
(n = 0 to 15, 30, 31)
H'FFFE5112
+ n × 32
Mailbox n Trigger Time_0
(n = 24 to 30)
MBn_TTT_0
(n = 24 to 30)
16
H'FFFE5114
+ n × 32
Mailbox n TT Control_0
(n = 24 to 29)
MBn_TTCONTROL_0 16
(n = 24 to 29)
H'FFFE5116
+ n × 32
Master Control Register_1
MCR_1
16
H'FFFE5800
General Status Register_1
GSR_1
16
H'FFFE5802
Bit Configuration Register 1_1
BCR1_1
16
H'FFFE5804
Bit Configuration Register 0_1
BCR0_1
16
H'FFFE5806
Interrupt Register_1
IRR_1
16
H'FFFE5808
Interrupt Mask Register_1
IMR_1
16
H'FFFE580A
Error Counter Register_1
TEC_REC_1
16
H'FFFE580C
Transmit Pending Register 1_1
TXPR1_1
16
H'FFFE5820
Transmit Pending Register 0_1
TXPR0_1
16
H'FFFE5822
Access
Size
16
16, 32
16
16, 32
16
8, 16, 32
8, 16
8, 16, 32
8, 16
8, 16
16
16
16
16
16
16
16
16
16
8, 16
32
16
Rev. 1.00 Mar. 25, 2008 Page 1635 of 1868
REJ09B0372-0100