SH7205 Datasheet, PDF (1552/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 I/O Ports
28.2.8 Port D Port Register L (PDPRL)
PDPRL is a 16-bit read-only register, in which the PD2PR to PD0PR bits correspond to the PD2
to PD0 pins, respectively. PDPRL always returns the states of the pins regardless of the PFC
setting.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
PD2 PD1 PD0
PR PR PR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0 PD2 PD1 PD0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W
15 to 3 —
All 0
R
2
PD2PR Pin state R
1
PD1PR Pin state R
0
PD0PR Pin state R
Description
Reserved
These bits are always read as 0 and cannot be
modified.
The pin state is returned regardless of the PFC setting.
These bits cannot be modified.
28.2.9 Port E Data Register L (PEDRL)
PEDRL is a 16-bit readable/writable register that stores port E data. The PE13DR to PE0DR bits
correspond to the PE13 to PE0 pins, respectively.
When a pin function is general output, if a value is written to PEDRL, that value is output from the
pin, and if PEDRL is read, the register value is returned regardless of the pin state.
When a pin function is general input, if PEDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PEDRL, although that value is written into PEDRL, it
does not affect the pin state. Table 28.6 summarizes PEDRL read/write operation.
Bit: 15
-
Initial value: 0
R/W: R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
DR DR DR DR DR DR DR DR DR DR DR DR DR DR
0
0
*
0
*
0
*
0
0
0
0
0
0
0
0
R R/W R R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Depends on the state of the external pin.
Rev. 1.00 Mar. 25, 2008 Page 1520 of 1868
REJ09B0372-0100