SH7205 Datasheet, PDF (276/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
Figure 9.1 shows the operand cache structure. The instruction cache structure is the same as the
operand cache structure except for not having the U bit.
Address array (ways 0 to 3)
Data array (ways 0 to 3)
Entry 0 V U Tag address
Entry 1
.
.
.
.
.
.
0 _LW0
1
.
.
.
.
.
.
LW1
LW2
LW3
LRU
0
1
.
.
.
.
.
.
Entry 127
127
23 (1 + 1 + 21) bits
128 (32 × 4) bits
LW0 to LW3: Longword data 0 to 3
Figure 9.1 Operand Cache Structure
127
6 bits
(1) Address Array
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid.
The U bit (only for operand cache) indicates whether the entry has been written to in write-back
mode. When the U bit is 1, the entry has been written to; when 0, it has not.
The tag address holds the physical address used in the external memory access. It consists of 21
bits (address bits 31 to 11) used for comparison during cache searches. In this LSI, the addresses
of the cache-enabled space are H'00000000 to H'1FFFFFFF, and therefore the upper three bits of
the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset but not initialized by a manual reset or in
standby mode. The tag address is not initialized by a power-on reset, manual reset, or in standby
mode.
(2) Data Array
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes).
The data array is not initialized by a power-on reset, manual reset, or in standby mode.
Rev. 1.00 Mar. 25, 2008 Page 244 of 1868
REJ09B0372-0100