SH7205 Datasheet, PDF (1119/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
23, 22 —
All 0
21, 20 FIFOTRG 00
[1:0]
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W FIFO Trigger Setting
Specify the condition (the byte number) for generation
of FLDTFIFO and FLECFIFO transfer requests.
• In flash-memory read
Issue an interrupt to the CPU or issue a DMA
transfer request when FLDTFIFO (FLECFIFO)
stores the following number of bytes or more:
00: 4 (4)
01: 16 (16)
10: 128 (4)
11: 128 (16)
• In flash-memory programming
Issue an interrupt to the CPU or issue a DMA
transfer request when FLDTFIFO (FLECFIFO) has
the following empty area of bytes or more:
00: 4 (4)
01: 16 (16)
10: 128 (4)
11: 128 (16)
Note: For DMA transfer, set the same number as that of
the single operand transfer data count (OPSEL).
19
AC1CLR 0
R/W FLECFIFO Clear
Clears FLECFIFO.
0: Retains the FLECFIFO value. In flash-memory
access, this bit should be cleared to 0.
1: Clears FLECFIFO. After FLECFIFO has been
cleared, this bit should be cleared to 0.
Rev. 1.00 Mar. 25, 2008 Page 1087 of 1868
REJ09B0372-0100