SH7205 Datasheet, PDF (304/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.1 CSn Control Register (CSnCNT) (n = 0 to 5)
CSnCNT selects the width of the external bus and controls the operation of the CSC interface.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
BSIZE[1:0]
-
-
- EXENB
Initial value: 0
0
0
0
0
0
0
0
0
0
0*¹ 0 *¹ 0
0
0
0 *²
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R
R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 22 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
21, 20 BSIZE[1:0] 00*¹ R/W External Bus Width Select
These bits specify the width of the data bus for the
external device corresponding to a CSC channel. The
initial value for the data bus width for CSC channel 0
(CS0) differs depending on the MD0 pin setting.
10: 8-bit bus
00: 16-bit bus
01: 32-bit bus
19 to 17 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
16
EXENB 0*²
R/W Operation Enable
This bit enables or disables the operation for each
corresponding CSC channel. The initial value
corresponding to CS0 only is operation enabled (EXENB
= 1).
0: Operation disabled
1: Operation enabled
Rev. 1.00 Mar. 25, 2008 Page 272 of 1868
REJ09B0372-0100