SH7205 Datasheet, PDF (372/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
• Multiple Write Timing Setting Examples
Figures 10.32 to 10.34 show the correspondence between the timing of multiple write operations
involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table 10.12
lists the SDRAMm timing register (SDmTR) set values for each figure.
Table 10.12 SDITR Set Value Correspondence Table (Multiple Write Timing)
Figure
Figure 10.32
Figure 10.33
Figure 10.34
DRAS
010
000
000
DRCD
00
01
01
DPCG
001
001
001
DWR
0
0
1
Multiple writes
CKIO
SDRAM command
ACT WR WR WR WR PRA DSL
Data bus
d0
d1
d2
d3
DRCD
(ACT-WR)
DWR
DPCG
(WR-PRA) (PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all-banks command
DSL: Deselect command
Figure 10.32 Multiple Write Timing Example 1
Rev. 1.00 Mar. 25, 2008 Page 340 of 1868
REJ09B0372-0100