SH7205 Datasheet, PDF (1512/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 27 Pin Function Controller (PFC)
Table 27.9 Multiplexed Pins (Port J)
Setting
Register
PJCRL4
PJCRL3
PJCRL2
PJCRL1
Setting of Mode Bits (PJnMD[3:0])
0000
0001
0010
0011
0100
0101
Function 1
(General I/O)
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
Function 5
(Related Module)
Function 6
(Related Module)
PJ12 output (port)
VIDATA7 input
(Video-In)
SCS1 I/O (SSU)

FRB input (FLCTL) 
PJ11 I/O (port)
VIDATA6 input
SSO1 I/O (SSU)



(Video-In)
PJ10 I/O (port)
VIDATA5 input
SSI1 I/O (SSU)



(Video-In)
PJ9 I/O (port)
VIDATA4 input
SSCK1 I/O (SSU) 


(Video-In)
PJ8 I/O (port)
VIDATA3 input
(Video-In)
TIOC1B I/O (MTU2) 
NAF7 I/O (FLCTL) 
PJ7 I/O (port)
VIDATA2 input
(Video-In)
TIOC1A I/O (MTU2) 
NAF6 I/O (FLCTL) 
PJ6 I/O (port)
VIDATA1 input
TEND3 output

(Video-In)
(DMAC)
FCE output (FLCTL) 
PJ5 I/O (port)
VIDATA0 input
(Video-In)
DACK3 output
(DMAC)
DACT3 output
(DMAC)
FSC output (FLCTL) TxD4 output (SCIF)
PJ4 I/O (port)
VICLK input
(Video-In)
DREQ3 input

(DMAC)
FOE output (FLCTL) RxD4 input (SCIF)
PJ3 I/O (port)
IRQ7 input (INTC) TIOC0D I/O (MTU2) 

TxD3 output (SCIF)
PJ2 I/O (port)
IRQ6 input (INTC) TIOC0C I/O (MTU2) 

RxD3 input (SCIF)
PJ1 I/O (port)
IRQ5 input (INTC) TIOC0B I/O (MTU2) 


PJ0 I/O (port)
IRQ4 input (INTC) TIOC0A I/O (MTU2) 


Table 27.10 Multiplexed Pins (Port K)
0000
Setting Function 1
Register (General I/O)
PKCRL1 PK1 I/O (port)
PK0 I/O (port)
Setting of Mode Bits (PKnMD[3:0])
0001
0010
0011
Function 2
(Related Module)
Function 3
(Related Module)
Function 4
(Related Module)
DCLKIN input


(Video-Out)
CSYNC output


(Video-Out)
0100
Function 5
(Related Module)
FCDE output
(FLCTL)
FWE output (FLCTL)
Rev. 1.00 Mar. 25, 2008 Page 1480 of 1868
REJ09B0372-0100