SH7205 Datasheet, PDF (325/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)
SDmADR specifies the data bus width and the channel size for SDRAM.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DDBW[1:0]
-
-
-
-
-
DSZ[2:0]
Initial value: 0
0
0
0
0
0
-
-
0
0
0
0
0
-
-
-
R/W: R
R
R
R
R
R R/W R/W R
R
R
R
R R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 10 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
9, 8
DDBW Undefined R/W SDRAM Data Bus Width Setting
[1:0]
These bits specify the width of the SDRAM data bus.
When accessing 32-bit data in SDRAM with a 16-bit bus
width, the 16 bits at the first half of the address (A1 = 0)
are accessed first, and then the 16 bits at the second half
of the address (A1 = 1) are accessed.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
7 to 3 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 293 of 1868
REJ09B0372-0100