SH7205 Datasheet, PDF (1392/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Bit
Bit name
5, 4
SB_FMT
3 to 1 
0
SA_FMT
Initial
Value
R/W
00
R/W
Undefined R
0
R/W
Description
SB Image Format
These bits specify the format of an image sent to SB.
00: αRGB444 (16 bits)
01: αRGB555 (16 bits)
10: α (4 bits)
11: Reserved
Reserved
The read value is undefined. The write value should
always be 0.
SA Image Format
This bit specifies the format of an image data sent to
SA.
0: αRGB444 (16 bits)
1: αRGB555 (16 bits)
• If the SB_FMT bits are set to 10, the SSWIDH bits in GR_SABSET should be set as follows:
In 16-bit access: For the SSWIDH bits in GR_SABSET, the minimum number of pixels to be
transferred and the pixel transfer unit should be set to 4 and 4 × n (n: arbitrary
integer), respectively. Setting 2 or 3 pixels to these bits is prohibited.
In 32-bit access: For the SSWIDH bits in GR_SABSET, the minimum number of pixels to be
transferred and the pixel transfer unit should be set to 8 and 8 × n (n: arbitrary
integer), respectively.
Rev. 1.00 Mar. 25, 2008 Page 1360 of 1868
REJ09B0372-0100