SH7205 Datasheet, PDF (262/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
7, 6
CD[1:0]
00
R/W C Bus Cycle/I Bus Cycle Select
Select the C bus cycle or I bus cycle as the bus cycle of
the break condition.
00: Condition comparison is not performed.
01: Break condition is the C bus (F bus or M bus) cycle.
10: Break condition is the I bus cycle.
11: Break condition is the C bus (F bus or M bus) cycle.
5, 4
ID[1:0]
00
R/W Instruction Fetch/Data Access Select
Select the instruction fetch cycle or data access cycle
as the bus cycle of the break condition. If the
instruction fetch cycle is selected, select the C bus
cycle.
00: Condition comparison is not performed.
01: Break condition is the instruction fetch cycle.
10: Break condition is the data access cycle.
11: Break condition is the instruction fetch cycle or data
access cycle.
3, 2
RW[1:0]
00
R/W Read/Write Select
Select the read cycle or write cycle as the bus cycle of
the break condition.
00: Condition comparison is not performed.
01: Break condition is the read cycle.
10: Break condition is the write cycle.
11: Break condition is the read cycle or write cycle.
1, 0
SZ[1:0]
00
R/W Operand Size Select
Select the operand size of the bus cycle for the break
condition.
00: Break condition does not include operand size.
01: Break condition is byte access.
10: Break condition is word access.
11: Break condition is longword access.
Rev. 1.00 Mar. 25, 2008 Page 230 of 1868
REJ09B0372-0100