SH7205 Datasheet, PDF (148/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
(7) Frequency Control Register 0 (FRQCR0)
The frequency control register 0 (FRQCR0) has control bits assigned for the following functions:
clock output/non-output from the CKIO pin during software standby mode, the frequency
multiplication rate of the PLL circuit, and the frequency division ratio of the CPU0 internal clock
(I₀φ) and the peripheral clock (Pφ).
(8) Frequency Control Register 1 (FRQCR1)
The frequency control register 1 (FRQCR1) has control bits assigned for the following function:
frequency division ratio of the CPU1 internal clock (I₁φ).
Rev. 1.00 Mar. 25, 2008 Page 116 of 1868
REJ09B0372-0100