SH7205 Datasheet, PDF (925/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value R/W Description
9
PDTA
0
R/W • DWL = 010, 011, 100, 101 (with a data word length
of 18, 20, 22 or 24 bits), PDTA = 0 (left-aligned)
The data bits used in SSIRDR or SSITDR are the
following:
Bits 31 down to (32 minus the number of bits in the
data word length specified by DWL).
That is, If DWL = 011, the data word length is 20
bits; therefore, bits 31 to 12 in either SSIRDR or
SSITDR are used. All other bits are ignored or
reserved.
• DWL = 010, 011, 100, 101 (with a data word length
of 18, 20, 22 or 24 bits), PDTA = 1 (right-aligned)
The data bits used in SSIRDR or SSITDR are the
following:
Bits (the number of bits in the data word length
specified by DWL minus 1) to 0
i.e. if DWL = 011, then DWL = 20 and bits 19 to 0
are used in either SSIRDR or SSITDR. All other bits
are ignored or reserved.
• DWL = 110 (with a data word length of 32 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus.
8
DEL
0
R/W Serial Data Delay
0: 1 clock cycle delay between SSIWS and SSIDATA
1: No delay between SSIWS and SSIDATA
Rev. 1.00 Mar. 25, 2008 Page 893 of 1868
REJ09B0372-0100