SH7205 Datasheet, PDF (955/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

(1) Reception Using DMA Controller
Section 19 Serial Sound Interface with FIFO (SSIF)
Start
Release from reset,
set SSICR configuration bits.
Setup DMA controller
to transfer data
from SSIF module to memory.
Enable SSIF module,
enable DMA,
enable error interrupts.
Wait for interrupt from DMAC or SSIF.
Set TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
UIEN = 1, OIEN = 1,
RIE = 1
Yes
SSIF error interrupt?
No
No
DMAC:
End of Rx data?
Yes
Yes
More data to be sent?
No
Disable SSIF module,
disable DMA,
disable error interrupts,
enable idle interrupt.
EN = 0,
UIEN = 0, OIEN = 0,
IIEN = 1, RIE = 0
Wait for idle interrupt
from SSIF module.
End*
Note: * If the SSIF encounters an error interrupt underflow/overflow,
go back to the start in the flowchart again.
Figure 19.22 Reception Using DMA Controller
Rev. 1.00 Mar. 25, 2008 Page 923 of 1868
REJ09B0372-0100