SH7205 Datasheet, PDF (1391/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.11 Pixel Format Setting Register for Graphics (GR_PIXLFMT)
The register GR_PIXLFMT sets the pixel formats which are used for the input and output buffers.
The SE_FMT bit is applied to the 2DG in synchronization with the VSYNC signal. Bits other than
the SE_FMT bit are applied to the 2DG immediately.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SE_
FMT
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
DC_
FMT
-
-
SB_FMT
-
-
-
SA_
FMT
Initial value: -
-
-
-
-
-
-
0
-
-
0
0
-
-
-
0
R/W: R
R
R
R
R
R
R R/W R
R R/W R/W R
R
R R/W
Bit
Bit name
31 to 17 
16
SE_FMT
15 to 9 
8
DC_FMT
7, 6

Initial
Value
R/W
Undefined R
0
R/W
Undefined R
0
R/W
Undefined R
Description
Reserved
The read value is undefined. The write value should
always be 0.
SE Image Format
This bit specifies the format of an image data sent to
SE.
0: αRGB444 (16 bits)
1: αRGB555 (16 bits)
Reserved
The read value is undefined. The write value should
always be 0.
DC Image Format
This bit specifies the format of an image data sent
from DC.
0: αRGB444 (16 bits)
1: αRGB555 (16 bits)
Reserved
The read value is undefined. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1359 of 1868
REJ09B0372-0100