SH7205 Datasheet, PDF (1630/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 User Debugging Interface (H-UDI)
31.6 Boundary Scan
By setting the commands in BSIR by the H-UDI, the H-UDI pins can be configured for boundary
scan mode defined by JTAG.
31.6.1 Supported Instructions
This LSI supports three required instructions (BYPASS, SAMPLE/PRELOAD, and EXTEST) and
three optional instructions (IDCODE, CLAMP, and HIGHZ) defined by JTAG.
(1) BYPASS
The BYPASS instruction is a required standard instruction to operate the bypass register. This
instruction is used to increase the transfer speed of serial data of other LSIs on the printed circuit
board by reducing the shift path. During execution of this instruction, the test circuit does not
affect the system circuit.
(2) SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction inputs a value from the internal circuit of the LSI to the
boundary scan register, and output the data from scan path or load the data to the scan path.
During execution of the instruction, the value on the input pin of the LSI is transferred to the
internal circuit and the value of the internal circuit is output externally from the output pin.
Execution of the instruction does not affect the system circuit of the LSI.
In SAMPLE operation, the snapshots of the value transferred from the input pin to the internal
circuit and the value transferred from the internal circuit to the output pin are captured in the
boundary scan register and then read from the scan path. Capturing of the snapshots is performed
in synchronization with the rising edge of TCK in the capture-DR state. The capturing is
performed without interfering with normal operation of the LSI.
In PRELOAD operation, an initial value is set in the output latch of the boundary scan register
from the scan path before execution of the EXTEST instruction. Without PRELOAD operation, an
undefined value is output from the output pin until the first scan sequence is completed
(transferred to the output latch) during execution of the EXTEST instruction (the parallel output
latch is always output to the output pin with the EXTEST instruction).
Rev. 1.00 Mar. 25, 2008 Page 1598 of 1868
REJ09B0372-0100