SH7205 Datasheet, PDF (1310/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
(2) FIFO Buffer Clearing
Table 24.22 summarizes the clearing of the FIFO buffer by this module. The FIFO buffer can be
cleared using the three bits shown below.
Table 24.22 List of Buffer Clearing Methods
Bit Name
Register
Function
Clearing
method
BCLR
CFIFOCTR
DnFIFOCTR
Clears the FIFO
buffer on the CPU
side
Clear by writing 1 to
this bit
DCLRM
DnFIFOSEL
ACLRM
PIPEnCTR
In this mode, the FIFO buffer
is cleared automatically after
the data of the specified pipe
has been read.
This is the auto buffer clear
mode, in which all of the
received packets are
discarded.
1: Mode enabled
1: Mode enabled
0: Mode disabled
0: Mode disabled
(3) FIFO Port Functions
Table 24.23 shows the settings for the FIFO port functions of this module. In write access, writing
data until the buffer is full (or the maximum packet size for non-continuous transfers)
automatically enables sending of the data to the USB bus. To enable sending of data before the
buffer is full (or before the maximum packet size for non-continuous transfers), the BVAL bit in
C/DnFIFOCTR must be set to signal that the writing has ended. Also, to send a zero-length
packet, the BCLR bit in the same register must be used to clear the buffer and then the BVAL bit
set in order to signal the end of writing.
In read access, reception of new packets is automatically enabled if all of the data has been read.
Data cannot be read when a zero-length packet is being received (DTLN = 0), so the BCLR bit in
the register must be used to release the buffer. The length of the data being received can be
confirmed using the DTLN bit in C/DnFIFOCTR.
Rev. 1.00 Mar. 25, 2008 Page 1278 of 1868
REJ09B0372-0100