SH7205 Datasheet, PDF (790/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.4 Bit Rates and SCBRR Settings (Asynchronous Mode, BGDM = 0, ABCS = 0) (4)
Pφ (MHz)
Bit Rate
(bit/s)
n
30
N
Error (%) n
110
3
132
0.13
3
150
3
97
−0.35
3
300
2
194
0.16
2
600
2
97
−0.35
2
1200
1
194
0.16
1
2400
1
97
−0.35
1
4800
0
194
−1.36
0
9600
0
97
−0.35
0
19200
0
48
−0.35
0
31250
0
29
0.00
0
38400
0
23
1.73
0
Note: Settings with an error of 1% or less are recommended.
33
N
145
106
214
106
214
106
214
106
53
32
26
Error (%)
0.33
0.39
−0.07
0.39
−0.07
0.39
−0.07
0.39
−0.54
0.00
−0.54
Rev. 1.00 Mar. 25, 2008 Page 758 of 1868
REJ09B0372-0100