SH7205 Datasheet, PDF (1629/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 User Debugging Interface (H-UDI)
TCK
TDO
(after execution of TDO transition
timing switching command)
TDO
(initial value)
t_TDOD
t_TDOD
Figure 31.3 H-UDI Data Transfer Timing
31.5.4 H-UDI Reset
An H-UDI reset occurs when an H-UDI reset assert command is set in SDIR. An H-UDI reset is
of the same kind as a power-on reset. An H-UDI reset is cleared by setting an H-UDI reset negate
command. The required time between the H-UDI reset assert command and H-UDI reset negate
command is the same as time for keeping the RES pin low to apply a power-on reset.
SDIR
H-UDI reset assert
H-UDI reset negate
Chip internal reset
CPU state
Fetch the initial values of PC and SR from
the exception handling vector table
Figure 31.4 H-UDI Reset
31.5.5 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in
SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in fetching the
exception service routine start address from the exception handling vector table, jumping to that
address, and starting program execution from that address. This interrupt request has a fixed
priority level of 15.
H-UDI interrupts are accepted in sleep mode, but not in software standby mode.
Rev. 1.00 Mar. 25, 2008 Page 1597 of 1868
REJ09B0372-0100