SH7205 Datasheet, PDF (478/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
DMA request (ch0)
DMA request (ch1)
DMA request (ch2)
DMA request (ch3)
Mask period
Mask period
Mask period
DMA acceptance ^{ch2DMA ch3DMA ch0DMA ch2DMA ch3DMA}
channel
[1]
[2]
[3]
[4]
ch0, ch2, and ch3 are set to a level sense.
ch1 is set to an edge sense.
ch0DMA ch1DMA ch1DMA ch3DMA ch3DMA
[5]
[6]
[7]
[8]
[9]
Thick lines indicate the DREQ bit status.
Figure 11.11 Example of Outline Operation When Multiple DMA Requests Occur
Rev. 1.00 Mar. 25, 2008 Page 446 of 1868
REJ09B0372-0100