SH7205 Datasheet, PDF (1362/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3 Register Descriptions
The 2DG has the following registers. During operation in synchronization with the VSYNC
signal, register values are applied to the 2DG when the VSYNC signals are low pulse. However,
the read/write to the applicable register is irrelevant to the VSYNC synchronization.
Table 26.2 Configuration of Registers
Register Name
Abbreviation
Blit function setting register for GR_BLTPLY
graphics
Mixing function setting register GR_MIXPLY
for graphics (synchronized with
VSYNC)
Operation status register for
graphics
GR_DOSTAT
Interrupt status register for
graphics
GR_IRSTAT
Interrupt mask control register GR_INTMSK
for graphics
Interrupt reset control register GR_INTDIS
for graphics
DMAC-request control register GR_DMAC
for graphics
Source A&B read-in-area setting GR_SABSET
register for blitter
Destination C write area setting GR_DCSET
register for blitter
Source E read-in area setting
register for output block
(synchronized with VSYNC)
MGR_SESET
Pixel format setting register for GR_PIXLFMT
graphics (only one bit, SE_FMT,
is synchronized with VSYNC)
Operation mode setting register GR_BLTMODE
for blitter
Resize display setting register GR_RISZSET
for graphics
R/W
R/W
R/W
R
R
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value Address
Access
Size
H'00000000 H'E8000000 16, 32
H'00000000 H'E8000004 16, 32
H'00000000 H'E8000008 16, 32
H'00000000 H'E800000C 16, 32
H'00007171 H'E8000010 16, 32
H'00000000 H'E8000014 16, 32
H'30000010 H'E8000020 16, 32
H'00000000 H'E8000030 16, 32
H'00000001 H'E8000038 16, 32
H'00000000 H'E8000040 16, 32
H'00000000 H'E8000048 16, 32
H'00000000 H'E8000050 16, 32
H'00010300 H'E8000060 16, 32
Rev. 1.00 Mar. 25, 2008 Page 1330 of 1868
REJ09B0372-0100