SH7205 Datasheet, PDF (1498/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
SBHF_STAT(0)
SBHF_STAT(1)
Interrupt event setting pulse
An interrupt event occurs (1-1)
An interrupt event is reset (1-6)
Interrupt event resetting pulse
The INT_SHFUL bits of
the GR_IRSTAT register
The INQ_SHFUL bits of
the GR_IRSTAT register
The DIS_SHFUL bits of
the GR_INTDIS register
Interrupt signal (negative logic)
(1-2)
(1-2)
(1-2)
(1-5)
(1-7)
(1-7)
(1-5)
(1-4)
CPU operation
Recognizes the occurrence Reads from the
Writes to the interrupt reset
of an interrupt (1-3) interrupt status register (1-3) control register (1-4)
Figure 26.57 Interrupt Handling (1)
Rev. 1.00 Mar. 25, 2008 Page 1466 of 1868
REJ09B0372-0100