SH7205 Datasheet, PDF (1437/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Figure 26.16 shows an example of data transfer to the SB buffer using the DMAC.
Internal clock
(66 MHz)
DMA3 request
DMA3 acknowledge
Transfer data
32 data Transfer
(one operand)
32 data Transfer
(one operand)
32 data Transfer
(one operand)
SB buffer full
Processing 1 in the 2DG
Processing 2 in the 2DG
Data being
processed in the
graphics block
Data transfer to
the DC buffer
Data being
processed in the
graphics block
(The SB buffer can store up to 64 data items.
Accordingly, when 64 data items have been input to the buffer, the transfer request is suspended.
The data transfer is resumed when processing of the 64 data items has been completed.)
Figure 26.16 96-item Data Transfer Timing in Dual/Single Address Transfer Mode
(Single-Operand Transfer)
Rev. 1.00 Mar. 25, 2008 Page 1405 of 1868
REJ09B0372-0100