SH7205 Datasheet, PDF (394/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
 Non-stop transfer: Transfers data until the byte count reaches "0" per DMA request.
Does not arbitrate channels.
Requires only the first request trigger.
• Channel priorities: Channel 0 > channel 1 > ... > channel 12 > channel 13 (this priority order is
fixed)
• Interrupt request: Two types of interrupt requests (generated when the byte counter reaches
"0")
 Interrupt request signal for each channel
 Interrupt request signal common to multiple channels
• Reload function: Reloads the source address, destination address, and byte count.
• Rotate function: The address rotate function can be set.
• Two-dimensional addressing: This can be specified in channels 0 to 7.
• The DMAC suspend/restart/stop function can be set.
Note:
Terminologies in this section are defined as follows:
Single data transfer: Transfer in one read cycle or one write cycle by the DMAC
Single operand transfer: Continuous data transfer by the DMAC on one channel (amount
of data to be transferred is set in a register)
Single DMA transfer: Transfer of data by the number of data set in the byte count register
from the start address to the end address
Channel number: n = 0 to 13
Two-dimensional addressing-supported channel number: m = 0 to 7
Request source number: k = 0 to 52
Rev. 1.00 Mar. 25, 2008 Page 362 of 1868
REJ09B0372-0100