SH7205 Datasheet, PDF (72/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Classification Symbol
I/O
AND/NAND
FRB
I
flash memory
controller
(FLCTL)
FWE
O
NAF7 to NAF0 I/O
USB2.0
DP1, DP0
I/O
host/function
DM1, DM0
I/O
module (USB)
VBUS
I
REFRIN
I
USB_X1
I
USB_X2
O
USBAPVcc
I
USBAPVss
I
USBAVcc
I
USBAVss
I
USBDVcc
I
Name
Function
Flash memory
ready/busy
Ready/busy: High level indicates
ready state and low level indicates
busy state.
Flash memory
write enable
Write enable: Flash memory latches
commands, addresses, and data on
the falling edge.
Flash memory
data
Data I/O pins.
USB D+ data USB bus D+ data.
USB D– data USB bus D– data.
VBUS input
Connected to Vbus on USB bus.
Reference input Connected to USBAPVss via
5.6±1%-kΩ resistance.
Crystal resonator/ Connected to a crystal resonator for
external clock for USB. An external clock signal may
USB
also be input to the USB_X1 pin.
Power supply for Power supply for pins.
transceiver
analog pins
Ground for
transceiver
analog pins
Ground for pins.
Power supply for Power supply for core.
transceiver
analog core
Ground for
transceiver
analog core
Ground for core.
Power supply for Power supply for core.
transceiver digital
core
Rev. 1.00 Mar. 25, 2008 Page 40 of 1868
REJ09B0372-0100